At work I am programming a VCO (Voltage Controlled Oscillator). This is a fancy name for a electronic device that takes in varying voltages and outputs corresponding frequencies. In the end, my group would like to control the output frequency of the VCO.

This requires programming a microcontroller (LPC1768) inside the VCO. A microcontroller is a “mini-computer.” This microcontroller is connected to a digital-to-analog converter (AD converter, AD5791). This two devices “talk” to each other over an SPI bus.


While learning how to program what the LPC1768 "says" to the AD5791, I learned about the clock polarities and phases that control how they talk to each other:

There are at least four actual lines that make-up the SPI bus. There is a line sending data (or "words") from the master (here a microcontroller), to the slave (digital-to-analog converter). This line is called MOSI (Master Out Slave In). The line sending data from the slave to the master is called MISO (Master In Slave Out). There is also a line the master and slave share called a clock. This literally functions as a clock - so they know when they can talk to each other. The last line is a chip select line. This line must be on when the master and slave are talking. Each slave the master is connected to generally has its own chip select line. Hence the uncertainty in the total number of lines that the SPI bus is composed of.

So the clock line is very important. Without this data would be sent and received chaotically, making the system faulty at best. The clock is just a repeative signal manifested as a varying voltage signal (like most electronic data).  Depending on the "rules" the clock follows data can be taken from the slave and master during certain times. The two variables the determine these rules are the polarity and phase of the clock (called CPOL and CPHA, respectively). CPOL determines the level of the idle clock state (when it is not receiving data). When CPOL is zero, that means when the clock voltage is low (usually 0V) the master and slave are not taking in data. When CPOL is one (the clock voltage is high), the master and slave are not taking in data. CPHA determines whether the data is taken on the leading (CPHA = 0) or trailing edge of the clock (CPHA = 1). The information on the MISO and MOSI lines can only change when the clock is idle and consequently must be stable when the clock is not idle. 

This site shows brilliant pictures of the four combinations of MISO and MOSI settings.

The ultimate goal of this VCO is to know the magnetic field of our magnet for Project 8. So we have a DPPH sample within the bore of the magnet. When this sample is irradiated with a specific frequency of EM radiation the nuclei of the sample flip spin. This is seen on an oscillscope by an energy absorption of the nuclei.